1. Field of the Invention
The present invention relates to the field of testing dynamic logic and related logic families such as N-NARY logic. More specifically, the present invention relates to stress testing dynamic logic and N-NARY logic.
2. Description of the Related Art
It is well known that the failure rate in a manufactured semiconductor device population is relatively high at the beginning of the operating life of the devices and decreases to a stable, lower failure rate for the remainder of the lifetime, increasing again at the end of the devices lifetime due to wear out mechanisms. Devices that fail early in their expected lifetime are said to experience infant mortality with these types of failures being called early life failures. Early life failures can be caused by latent defects, which are defects in the semiconductor device that are not detectable by normal initial testing. Early life failures cause problems for the manufacturers and consumers of semiconductors because by the time the early failures are detected, additional manufacturing cost has been invested in the final consumer product.
In order to reduce the infant mortality rate, the semiconductor device manufacturer attempts to accelerate the infant mortality failure mechanisms by a variety of different methods. Two of the most common methods for accelerating these latent defects are burn-in and stress testing. Burn-in generally involves operating each device in the device population at some specific temperature (usually a high temperature) for a certain amount of time (typically in the range of a few hours to a few days). Generally, bum-in is performed at a higher-than-usual voltage because it has been found that higher voltage accelerates defects. Following burn-in, the device population is tested to screen out the failed devices (if any). Stress testing, on the other hand, involves operating the device at a high voltage for a very short time and immediately testing the device afterwards for failure. Stress testing may be dynamic, in which clocks and signals switch under high voltage, or static, in which signals are held in a static state while high voltage is applied. For CMOS devices, static stress testing may also be accompanied by a current measurement test. This is because device current is very low when the device is in a quiescent state; current flow under high voltage is indicative of a defective or unreliable device. Either stress testing, burn-in, or both may be used to reduce early life failures of devices before or after the devices are shipped to consumers.
In order to reduce manufacturing costs and ensure quality outgoing products, it is important for burn-in and/or stress testing to accelerate failures in the most efficient and predictable way possible. It is therefore important that as many internal devices of the semiconductor device as possible be stressed during such testing. The extent that the device is exercised or stressed can be measured by the semiconductor device""s internal node toggle rates and coverage. Unfortunately, guaranteeing high node toggle rates and coverage is often compromised by several factors. First, device operation is often unreliable at extended temperature and/or voltage. Second, burn-in, and test hardware is more costly if it is required to exercise the devices with complex or lengthy test patterns.
The problem of reliably and efficiently exercising semiconductor devices under extended voltage and temperature conditions is made even more difficult when the device uses dynamic CMOS logic or related logic families. This is true because dynamic CMOS logic has reduced operational noise margins as compared to conventional static or complementary CMOS logic. These noise margins are further reduced at high voltage and high temperature because noise levels increase with higher voltage and sensitivity to noise increases at high temperature and high voltage. Additionally, high temperature reduces n-channel MOS threshold voltages, which make n-channel evaluate trees more sensitive to input-low noise. An advantage of using dynamic CMOS logic over complementary CMOS logic is that higher operating speeds are generally possible with dynamic logic. The noise margin problem of dynamic logic at extended voltage and/or temperature can be improved through various circuit design techniques, but these techniques usually involve some cost in terms of area, power, or operating frequency.
One of the most common noise problems in dynamic logic is the undesired discharge of a dynamic node. For n-channel evaluate trees this can be caused by noise on input signals to a gate that is supposed to be in the low state. Differential ground noise or noise coupled onto these input signals may cause the already slim ground noise margin to deteriorate further and eventually may cause device malfunction. Therefore, it can be seen that while dynamic CMOS logic offers speed advantages over conventional static or complementary CMOS logic, dynamic logic poses problems when required to operate at extended temperature or voltage conditions as required during burn-in or stress testing.
The present invention overcomes the above problems and provides dynamic logic and related logic families with the ability to operate at higher temperatures and voltages than previously possible. The present invention also provides greater coverage of exercised defects with minimal test patterns. This new operational mode increases the effectiveness of burn-in and stress testing for dynamic logic. EVSX, Inc. has invented a new logic family called N-NARY logic, which can be characterized as a fully-dynamic and self-synchronized logic family. N-NARY logic is more fully described in a patent application, U.S. Pat. Application Ser. No. 09/019355, filed Feb. 05, 1998 (05.02.1998), now U.S. Pat. No. 6,066,965, and titled xe2x80x9cMethod and Apparatus for a N-Nary logic Circuit Using 1- of -4 Encodingxe2x80x9d, which is incorporated by reference for all purposes and is referred to as xe2x80x9cThe N-nary Patent.xe2x80x9d It is noted that signals in this logic family are one- or zero-hot collections of 2 or more wires that are precharged and evaluate every cycle.
Additionally, the present invention is related to the logic synchronization techniques fully described in a patent application, U.S. Pat. Application Ser. No. 09/179330, filed Oct. 27, 1998 (27.10.1998), now U.S. Pat. No. 6,118,304, and titled xe2x80x9cMethod and Apparatus for Logic Synchronizationxe2x80x9d, which is incorporated by reference for all purposes.
Additionally, the present invention is related to the scannable logic techniques fully described in a patent application, U.S. Pat. App. Ser. No. 09/468,992, filed Dec. 21, 1999 (21.12.1999), now U.S. Pat. No. 6,271,683, and titled xe2x80x9cDynamic Logic Scan Gate Method and Apparatusxe2x80x9d, which is incorporated by reference for all purposes and is referred to as the xe2x80x9cScan Patentxe2x80x9d.
The present invention comprises a method and apparatus for N-NARY logic and dynamic logic that initializes the logic to a special stress mode. The present invention comprises a logic circuit that includes a shared logic tree with one or more evaluate nodes, one or more precharge devices, and an evaluate device. Coupled to the evaluate nodes is a state generation control circuit that generates a state signal. A state generation circuit receives the state signal from the state generation control circuit and initializes the evaluate nodes to a functionally illegal state that initializes the logic circuit to a special stress mode. One embodiment of the present invention initializes the evaluate nodes to a low state. Additionally, the state generation circuit can further comprise additional functions such as scan and reset. And, the present invention can comprise N-NARY logic and or dynamic logic. When the first logic circuit in a series of logic circuits is initialized to the functionally illegal state, the present invention will initialize the succeeding logic circuits in the series as each phase in the different clock domains evaluate, which initializes the succeeding logic circuits to the special stress mode.